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end component;

component B is ---- ocae ooea B port (Bx : in bit_vector(0 to 7); By : out bit_vector(0 to 15));

end component;

begin ---- oee poecco, oo A port map(X,Lab); ---- opea ooea cce B port map(Lab,Y); ---- opea ooea cce end System_AB;

Ta opao, oeee ooeo ccey oepyec ocae epeco epeae cooecyx ae cao ooea.

Ec coee coyc oee ee , o cooecye epeee oy e o . Bce aee ec aao. Ho ceye ae, o pyooe pecaee cao, oa oo cooecye cxee, oee, e ooe. o cao c e, o eco ooo co p oopeeo ee ecox cao pye pec opaaa oeo ce N co.

B ece popa oepaop port map acac yp apxeypoo ea a oepaopa poecco. peea pepe ac oepaopa opeeec oo coocaee eeo oopae opo oca ooeo. To e caoe oo cea p oo eoo cooec, apep:

S1: A port map(Ay=>Lab, Ax=>X);

S2: B port map(By=>Y, Bx=>Lab);

o ec e pa po, a a cooece oeceaec coocaee e.

eepaop cao Cyaop A A AB B B Y SS0 F S1 SSSSSPc.5.2. pep cce eepaop-cyaop Puc. 5.2 puep cucme eepamop-cyamop p oepoa cxex ce a coo ypoe pecae opa oo cooa pye ax. Hapep, cooa epec :

type control is (mov, lda, ani,, hlt);

signal data_bus : control;

paa opa, a opao, pecaec eoeco e. Tao oxo oeae oepoae ocooae o opo oypoex eae. B eoopx cyax pe coo , apep, subtype control is integer range 0 to 31. o yoee o cpae c e o -a ypoe opo oo.

Paccop pep oepoa cce, cocoe yx ooeo: cyaopa eepaopa cao. p pao cce ocaoo poc (pc. 5.2).

eepaop oppye ae oepao A B c caa ypae ye pao cyaopa S0-S3.

Ha xoe cce ee peya Y. ooe "cyaop" aa a ycoo o o a coc 5.1.

Taa 5.S3 S2 S1 S0 y F 0 0 0 A 0 0 0 A + B 0 0 1 0 A B 0 0 1 1 0 1 0 AB 0 1 0 B 0 1 1 0 A B POOEHE TA. 5.S3 S2 S1 S0 y F 0 1 1 1 A B 1 0 0 0 A + B 1 0 0 A + B 1 0 1 0 B 1 0 1 1 AB 1 1 0 0 1 1 0 1 A + B 1 1 1 0 A + B 1 1 1 1 A aepa poxoe cao epe cxey cocae 57 c. poe cce a e oe aca e:

library vector;

use std.textio.all,vector.functions.all;

entity MFChip is port(s3:in bit;s2:in bit;s1:in bit;s0:in bit;

A:in bit_vector(1 to 8);B:in bit_vector(1 to 8);

Fun:out bit_vector(1 to 8));

end MFChip;

architecture Chip of MFChip is begin Proc: process(s3,s2,s1,s0,A,B) begin if (s3='0') and (s2='0') and (s1='0') and (s0='0') then Fun<=not(A) after 57 ns;end if;

if (s3='0') and (s2='0') and (s1='0') and (s0='1') then Fun<=not(A or B) after 57 ns;end if;

if (s3='0') and (s2='0') and (s1='1') and (s0='0') then Fun<=not(A) and B after 57 ns;end if;

if (s3='0') and (s2='0') and (s1='1') and (s0='1') then Fun<="00000000" after 57 ns;end if;

if (s3='0') and (s2='1') and (s1='0') and (s0='0') then Fun<=not(A and B) after 57 ns;end if;

if (s3='0') and (s2='1') and (s1='0') and (s0='1') then Fun<=not(B) after 57 ns;end if;

if (s3='0') and (s2='1') and (s1='1') and (s0='0') then Fun<=A xor B after 57 ns;end if;

if (s3='0') and (s2='1') and (s1='1') and (s0='1') then Fun<=A and not(B) after 57 ns;end if;

if (s3='1') and (s2='0') and (s1='0') and (s0='0') then Fun<=not(A) or B after 57 ns;end if;

if (s3='1') and (s2='0') and (s1='0') and (s0='1') then Fun<=not(A or B) after 57 ns;end if;

if (s3='1') and (s2='0') and (s1='1') and (s0='0') then Fun<=B after 57 ns;end if;

if (s3='1') and (s2='0') and (s1='1') and (s0='1') then Fun<=A and B after 57 ns;end if;

if (s3='1') and (s2='1') and (s1='0') and (s0='0') then Fun<="00000001" after 57 ns;end if;

if (s3='1') and (s2='1') and (s1='0') and (s0='1') then Fun<=A or not(B) after 57 ns;end if;

if (s3='1') and (s2='1') and (s1='1') and (s0='0') then Fun<=A or B after 57 ns;end if;

if (s3='1') and (s2='1') and (s1='1') and (s0='1') then Fun<=A after 57 ns;end if;

end process Proc;

end Chip;

library vector;

use std.textio.all,vector.functions.all;

entity Generator is port (O1,O2:out Bit_Vector(1 to 8);os0,os1,os2,os3:out bit);

end Generator;

architecture Gen of Generator is signal O11: bit_vector(1 to 8):="10101010";

signal O21: bit_vector(1 to 8):="01010101";

signal os01:bit:='1';signal os11:bit:='0';signal os21:bit:='1';signal os31:bit:='0';

begin process begin O11<=O11;O21<=O21;

os01<=os01;os11<=os11;os21<=os21;os31<=os31;

wait for 100 ns;

end process;

O1<=O11;O2<=O21;

os0<=os01;os1<=os11;os2<=os21;os3<=os31;

end Gen;

entity shema is end shema;

architecture Sh of shema is component MFChip Port(s3:in bit;s2:in bit;s1:in bit;s0:in Bit;

A,B,Fun:in bit_vector(1 to 8));

end component;

component Generator port (O1,O2:out bit_vector(1 to 8);os0,os1,os2,os3:out bit);

end component;

signal A,B,O1,O2,Fun:bit_vector(1 to 8);

signal s1,s2,s3,s0,os0,os1,os2,os3:bit;

begin process (O1,O2,os0,os1,os2,os3) begin A<=transport O1 after 5 ns;B<=transport O2 after 5 ns;

s0<=transport os0 after 5 ns;s1<=transport os1 after 5 ns;

s2<=transport os2 after 5 ns;s3<=transport os3 after 5 ns;

end process;

Generator port map(O1,O2,os0,os1,os2,os3);

MFChip port map(s3,s2,s1,s0,A,B,Fun);

end Sh;

Ca Si pecae a ece poo c peee pacpocpae cao o ooo ooea o pyoo 5 c. Ceye ae, o ocae cxex ce ee opeeee pyoc, ocoeo p oepoa ooao o.

5.2 Moepoae ooao o Moepoae peax oecx cxe aacy peye cooa oee, e yx ae coco. oco eeo e yepe cxe, epeae xo cooeacoe cocoe. Tpexay ccey {0, 1, Z} oo ca aoo oepoa oca ooeo . B oeeeco oe Z-coco oo cooecyee ece, ae oepoae caoc eoo. B eoopx cyax, cxo exooecx coopae, ca, o Z - oeca ea.

Cocoe eopeeeoc ee caapoe ooaee X aae ooao ccee eco epe oec ye. coco X ae oa opeeea y opao.

Caap o IEEE 1164, pee oepoa, ee ceyee ocae:

type std_ulogic is ( 'U', -- e apoa 'X', -- ycao eopeeeoe cocoe '0', -- ycao yeoe cocoe '1', -- ycao eoe cocoe 'Z', -- ycao cocoe cooo eaca 'W', -- cpoc cocoe eopeeeoc 'L', -- cpoc cocoe y 'H', -- cpoc cocoe e ' - ', -- cocoe epa );

B caapo coceo aee poee ocaec paoa y c coco ooao o. Too oce oo oycaec oepoae. Ec ocae y ocyecec aee, o ee aea aca ee pecaee, apep:

function "and" (l: std_ulogic, r: std_ulogic) return UX01 is begin return(and_table(l,r));

end "and";

Peya pao y and_table acaec ae ee aea a ocaa c eco ae, pecae e a coc:

constant and_table : stdlogic_table := ( -------------------------------------------------------------- U X 0 1 Z W L H ------------------------------------------------------------( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U'), -- U ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- X ( '0', '0', '0', '0', '0', '0', '0', '0', '0'), -- ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- Z ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X'), -- W ( '0', '0', '0', '0', '0', '0', '0', '0', '0'), -- L ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X'), -- H ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X') -- );

Toa p oe oa s := a and b, e a = X b = 1, epeea s pe aee X.

Aaoo opeec a coc pyx oecx apeecx y.

CCO TEPATP 1 Coeo . ., oe C. A. Moepoae cce. M.: Bc. ., 1998. 319 c.

2 Ax . H. Moepoae cex cce. .: Maocpoee, 1988. 223 c.

3 ao A. . Moepoae popoeccopx cce. M.: epoaoa, 1990. 143 c.

4 yeo A. H. Moepoae epax poexoo, popo cxe. M.: Bc. ., 1989. 320 c.

5 pecyx . H., Bopoe . B., e A. A. Pace eeo pox ycpoc.

M.: Bc. ., 1991. 526 c.

6 Cce aoapoaoo poepoa paoepoe: Cpao / o pe. .

. Hopeoa. M.: Pao c, 1986.

7 Apcpo . P. Moepoae pox cce a e VHDL. M.: Mp, 1992. 175 c.

8 J. Armstrong. Chip Level Modelling in VHDL. Prentice Hall, 1988. P. 148.

9 Louis Baker. VHDL Programming with Advanced Topics, John Wiley & Sons. New York, 1993.

10 Gunther Lehmann, Bernhard Wunder. Schaltungsdesign mit VHDL. Manfred Selz, Poing, 1994.

317 s.

11 Abstrakte Modellierung digitaler Schaltungen (VHDL vom funktionalen Modell bis zur Gatterebene) // K. ten Hagen. Springer, 1995.

12 Peter J. Ashenden. University of Adelaide, South Australia: ftp: // ftp.cs.adelaide.edu.au / pub / VHDL-Cookbook (Mac, PC, PS); ftp: // bears.ece.ucsb.edu pub / VHDL; ftp: // du9ds4.fb9dv.uniduisburg.de/pub/cad.

13 eyo H. H. Mpopoeccope cpeca cce. M.: Pao c, 1989. 288 c.

COEPAHE BBEEHE..........................................

1 OCHOBHE BOPOC MOEPOBAH POBX BCTEHX CCTEM..........

1.1 oecoe oepoae yoax yo...

1.2 Coco oecoo oepoa...............

2 OCAHE A VHDL.........................

2.1 Cpyypa VHDL ocae papao...........

2.2 Ocae epeca...........................

2.3 Apxeype ea.............................

2.4 Oepaop oo...............................

2.5 poecc......................................

2.6 T ax...................................

2.7 Oepa......................................

2.8 acc oeo................................

2.9 Apy......................................

2.10 y poeyp...........................

2.11 ae.......................................

2.12 Oepaop ypae..........................

2.13 aep cao.............................

3 MOEPOBAHE OECX CXEM............

3.1 Moepoae oaox cxe.............

3.2 Moepoae oceoaeocx cxe.........

4 MOEPOBAHE HA POBHE.......

MPOCXEM.......

5 MOEPOBAHE CCTEM.......................

5.1 Moepoae cxex coee...............

5.2 Moepoae ooao o...............

CCO TEPATP..............................

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