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Haaoe aee pepa oo cpoc ycao e xo caa Reset Set. Taoe ece oe cxpo acxpo. B ec popa oaec ee oa epeea ocaa. He oaa pep cxpoo ycao pepa o cay Set.

process (Clk) begin if Clk and Clk'event then -- po caa if Set then y <= true; -- y a boolean else y <= a and b;

end if;

end if;

end process;

pep cpoca ycao py o cay init:

process begin wait until Clk -- po Clk if init then y <= 7; -- y a integer else y <= a + b;

end if;

end process;

oeee acxpooo cpoca ycao ocaec eaco o ypae o aooy cay. poco oaec ee oo ycoe ece o oy yco.

Paccop pep cpoca ae cooa apaeo opaoe o cay Reset:

y <= false when Reset else a when Clk and Clk 'event else y;

ooe ocae pepa c acxpo cpoco acxpoo ycaoo, e opaoa cao eaca apaea, oo peca a, a oaao e:

process (Clk, Reset) begin if Reset then q <= false; -- y a boolean else if Clk and Clk'event then -- po clock q <= d;

end if;

end if;

end process;

procedure ff_async_set (signal Clk, a, Set: boolean;

signal q : out boolean) begin if Set then q <= true;

elsif Clk and Clk'event then -- po clock q <= a; -- o ax end if;

end;

o oca oeee acxpoo ycao acxpooo cpoca, poco oae opo yco oepaop:

q <= false when Reset else true when Set else d when Clk and Clk 'event;

-- Reset Set apaeo opaoe process (Clk, Reset, Set) begin if Reset then q <= false; -- q a boolean elsif Set then q <= true else if Clk and Clk'event then -- po clock q <= d;

end if;

end if;

end process;

o oca oeee acxpoo apy, ao ae epeey Set Reset cao paee.

apya ax oe oc c cooae oceoaex oepaopo:

process (Clk, load_ctl,load_data) begin if load_ctl = '1' then q <= load_data;

elsif rising_edge(Clk) then q <= d;

end if;

end process;

Ta opao, ocae pepa pao o apye ax, cpocy ycaoe cxox ae. B poecce oepoa eoxoo e eoe pecaee e oo o oe pao cxe, o o aoy py: cxpooy acxpooy oc ec.

4 MOEPOBAHE HA POBHE MPOCXEM p cocae poeo a eeo ae, cocoe pocxe coo cee epa, apep, C, C CC, eoxoo ooac oe oo e ypo.

Moe ypo epao cxe - o oeeeca oe oecoo oa. Tooe ocae aepe cao ax oex ocyecec e cooa oca oee oo ypo.

Ocoe peoa oe ypo epax cxe opypyc cey opao.

C e oye pao yopye cxe peee apaep xoo xoo o oo coepoa. cxo peooe, o cxea caa ec ao po, e oycaec ee eoo a oee poce cpyype p. Moe cxe peayec e oceoaeoc pooepa, ocax oy pao cxe, e oca eoo pecpooo ypo. Papao oe oe cooa ecoe oca, cpyype cxe, cea peee apa, a ae a coco apa coco.

oo, o e ooe pecaee peex apaepo cxe, oe oa e ocaoy cee eaa o pee.

Moe cxe oo ycoo pae a p ac: xoy, ype xoy.

Bxoa ac coep xoe cea a oeco xoo, pe peycao yepa cao, a ae ae eoc yco. Bype ac coep cea a ooe pooepa opao cao (popapyee cxe), a, aep cao ocox ypex ex. Bxoa ac coep cea a oeco xox cao x peee apaep. Cpyypa oe cxe ee p ax cocax: aepe cao, aa ep yoaoe paee cxe.

Cpe aepe cao oo e: pocy, opao c ex c oo p pee. poca aepa oepyec ye aepaoo aae oo epeeo caa pyoy cay. aepaoe aaee peayec oepaopo after.

aepa opao c pecaec coeae oepaopa aepaoo pcaa ocpy poecca. Bxoo apaep p o coyec a xoo cce cao ayca poecca. aepa ex c oo p pee - oee coa oe aep.

ee oepoa peec exa poecco. poxoee cao ax cxeax paccapaec ecoo ao. Ha epo pee aax ca aepaec xox xox ex. Bopo a cooecye "epao" ac cxe, e paec peee poyc ca aee opoa eo. Booa opaoa caa popopao cxe. pepo ao cxe oe pecp c pexca xoa caa cpopoa papee ac ax. pep c popopao opaoo: C apaeoo oceoaeoo oa-oa.



Moe cxe cpyypo oe pecaea e paa, a oe y pa a oy. a ye paa peayec oeo poecce oe oy oy.

y paa ooaa y poxoe cao ey ya-poecca. poe oo, a ye paa oe e coe yoaoe paee. py coa, oy ee ecoo xox ee y. Hapep, oy opaaae ca X, Y, Z.

Ho ec oc oeo a caa X Y, X Z, Y Z. Bo cyae ye paa ceye pae a p ac, a oy peaoa e pex oex poecco c cooecy cca cao yceoc.

Bpeee apaep xox xox cao pecac epoo pacopo aepo.

Te ca ocaec peeoe oepoae. peee epox aepe oo opopoa c oo oepaopo assert report, a a oae epooc poyc yc ao eoc. o, epy oepe, cao c peea peycao yepa, a ae c apyee peoa aee eoc caa. apaepo oepaopa assert ec paee yea a. Be ae oo cooa apy cao. apaepo oepaopa report ec oe cooee, aeoe oe a. Oo oa oepaopa coyc ece acac oceoaeo py a pyo. Oepaop opo peex apaepo oy ac ocae epeca apxeypoe eo oea poea. Oac ec epo apae oaa, o opo - oaa, oo paax ooo apxeypoo ea.

DMX QDQRG.

Q.

D07 QQDQDQ.

. QDDD.

.

DSSDD.

.

Clk DS_L Rst Pc.4.1. cooe paecoe ooaee C Pc. 4.1 cooe paecoe ooaee C Paccop pep papao poea. yc ee C, ay yecop co pecp (pc. 4.1). p pao C cey. epe eacx ocox xoa (D00-D07, D10-D17, D20-D27, D30-D37) oypyc a oco xo (Q0-Q7) o caa opa S0 S1.

oa cao opa opee cooecy xo, apep, ec S0 = 0 S1 = 0, o Qi = D0i; S0 = 1 S1 = 0, o Qi = D1i; S0 = 0 S1 = 1, o Qi=D2i; S0 = 1 S1 = 1, o Qi = D3i. ae c paoo a opao xoa acac xoo pecp Qi o poy caa Clk. Cpe ypoe oo caa e a acae ae. C acpoax ax eo pocxo o poy caa S_L. Bco ypoe caa Rst cpacae yeoe aee coepoe pecpa Qi.

oepoa eep ece epec C, a ocoe oca yopoa oo ocpo oeeecy oe. poee yoaoe paee pocxe ocpo pa oe poecco. Ha ocoe aaa y C oo e ceye ee ac: xoe aa ax yecop, co pecp xoe aa ax. B ao ace ca poxo cooecyy opaoy aepaec a eoopoe pe. O oox apao paa oe oaa a pc. 4.2.

poecc Mux cooecye oya ooo xox aao a xo pecpa c aepo pacpocpae Del_sel. poecc Load opaaae y apy ax pecp o cay Clk. Bpe ac ax Del_load. Co pecp yoao pa a cxey S_L Clk D0i D1i Del_sel Del_load Del_shift Del_out Mux Load Shift Out D2i D3i S0,SRst Pc.4.2. pa oe poecco C Pc. 4.2 pa oe poecco C ca ax ca ax, a a oepa ac ca eac py o pya apyc pa caa. Bpe ca ax Del_shift. Cea xox aao eoaeo po oeoy poeccy. Ho cey oe cxee, oo ec ee o ye Out cooecy ey poecc. Bpe poxoe caa o cooo pecpa o xoa cxe epe xoe pao Del_out.

o ocpoeoy pay eep oo coca poe cxe a e VHDL. Haoee poco apa poea, e e peex cea cao ce poecc oee o, oe e a:

package typedef is subtype byte is bit_vector (7 downto 0);

end;

use work.typedef.all;

entity Bis_data is port (clk,rst,s_l : boolean;

s0, s1 : bit;

d0, d1,d2, d3 : byte;

q : out byte);

end Bis_data;

architecture BIS of Bis_data is constant Del_sel, Del_load, Del_shift, Del_out : time := 10 ns;

signal reg,shft : byte;

begin process (clk,rst,s_l) begin if rst then -- acxpo cpoc reg <= x"00";

shft <= x"00";

elsif clk and clk'event then -- a apy case s0 & s1 is -- yecpoae when b"00" => reg <= d0 after Del_sel;

when b"10" => reg <= d1 after Del_sel;

when b"01" => reg <= d2 after Del_sel;

when b"11" => reg <= d3 after Del_sel;

end case;

if s_l and s_l'event then -- a ca shft <= shft rol 1 after Del_shift;

else shft <= reg after Del_load;

end if;

end if;

end process;

q <= shft after Del_out;

end BIS;

Ceye oe, o paccope e pep xopo oa o pao C e oe pec oepoa pao. o pao o oepoae, ao cooec c pao opee p poecca. Ec opeyec opo peex apaepo, o caaa eoxoo pec peey apay c yaa e pee xapaepca cao (pc. 4.3) "cpo" ee poe.





Ha peeo apae oaa ae ocox peex xapaepc, oopeeo apaa cppye p pao pocxe. B aa oe pee a xo acxpooo cpoca pocxe ocyae ca Rst, e aey eoc Rst. epe eoopoe pe, e oaaoe a apae, a xo D ocya ae. Haeee pe yepa ax ooaeo a DATA. a o pe oa oc apya ax pecp, epe yecop. oce oo, a ae a xoe yy e ycooe aee, epa DS, o caa S0 S1 pocxo op aaa, oypyeoo a xo pecpa. B eee pee Sel (pee yepa), p eex aex S0 S1 o poy caa Clk pocxo ca ax pecpe.

URst Rst UDi DATA Bxoe ae * US0,S1 * DS Sel Bop * * UClk SC Clk UQ LOAD ae ae * US_L SHIFT LS SL Pc. 4.3 Bpeea apaa pao C Pc.4.3. Bpeea apaa pao C Haeee pe ey ocyee cao S0 S1 poo Clk ooaeo a SC.

eoc yca ac oa e ee Clk. B eee pee LOAD ae acac pecp. epe epa pee, aeee aee oopoo pao LS, oycaec c ax o poy S_L. Oepa ca oe poeea e oaeo oo oce ac ox ax. Maa eoc caa ca - SL. Opaoae a opao ae oc a xoax pocxe e eee, e epe pe SHIFT.

poe a e VHDL cooec c pao oe poepo eoopx peex apaepo oaa e.

package typedef is subtype byte is bit_vector (7 downto 0);

end;

use work.typedef.all;

entity Bis_data is generic(Trst,Tsel,Tclk,Tsl : time);

port (clk,rst,s_l : boolean;

s0, s1 : bit;

d0, d1,d2, d3 : byte;

q : out byte);

end Bis_data;

architecture BIS of Bis_data is constant Del_sel, Del_load, Del_shift, Del_out : time := 10 ns;

variable F : integer;

signal reg,shft : byte;

begin F:=0;

Reset: process(rst) assert rst'stable(Trst) report "Error Trst" if rst then -- acxpo cpoc reg <= x"00";

shft <= x"00";

end if;

end process Reset;

Load: process (clk) begin if clk'delay(Tclk)='1' and --Clk=1 eee Tclk not clk'delay(Tclk)'stable then -- epe e cae, o po assert s0'stable(Tsel) and --ec ca opa ca, o s1'stable(Tsel) --apya, ae o cooe report "Error Tsel" if s0'stable(Tsel) and s1'stable(Tsel) then case s0 & s1 is -- yecpoae when b"00" => reg <= d0 after (Del_sel+Del_load);

when b"10" => reg <= d1 after (Del_sel+Del_load);

when b"01" => reg <= d2 after (Del_sel+Del_load);

when b"11" => reg <= d3 after (Del_sel+Del_load);

end case; F:=1;

end if;

end if;

end process Load;

Shift: process (s_l) if s_l='1' and s_l'stable(Tsl) then -- a ca shft <= shft rol 1 after Del_shift;

end if;

F:=3;

end process Shift;

Out: process if F=3 then q <= shft after Del_out;

else q <= reg after Del_out;

end if;

F:=0;

end process Out;

end BIS;

Ta a e poeyooo xpae ax oce yecopa, o e y yecpoa apy oee oy oope poee oo poecce. Oeo aca poecc acxpooo cpoca.

poecc Out e ee cao ayca ooy cea ae. B poecce oepoa poepc oo aoee ae peee xapaepc. o eoc yco caoc cao oya.

5 MOEPOBAHE CCTEM Moepoae cce ee a ocox acea pee aa. Bo-epx, ce oe pecae a oee coo oeeeco ypoe. o cooecye a ooea, a popoeccop, pocxe a, epece C .. Bo-opx, ce ooe cce oee cxeo coee, oa o a, cce acpa oe c. Ta opao, p oepoa cce oa yac cea ooeo eococ ce cce.

5.1 Moepoae cxex coee B e VHDL oe coee ooeo epea pea opa pecaec e apxeypoo ea c ocae epeca ooeo. Paccop pep cce (pc. 5.1), cocoe yx ooeo A B, coeex oao o LAB. yc oaa a ee oce pooo. Ccea ee oce xox xox.

Ccea ooe A ooe B X L Y AB Ax Ay Bx By Pc. 5.1 Cpyypa cxea cce yx ooeo Pc.5.1. Cpyypa cxea cce x yx ooe Toa epec ooeo A B ee ceyee ocae:

entity A is port (Ax : in bit_vector(0 to 7); Ay : out bit_vector(0 to 7));

end A;

entity B is port (Bx : in bit_vector(0 to 7); By : out bit_vector(0 to 15));

end B;

Ocae cce ae ee epec apxeypoe eo, oopo acaec epec ooea opea ce ey ooea. paccapaeo pepe cce oo aca:

entity System is port (X : in bit_vector(0 to 7); Y : out bit_vector(0 to 7));

end System;

architecture System_AB of System is signal Lab : bit_vector(0 to 7); ----ocae c component A is ---- ocae ooea A port (Ax : in bit_vector(0 to 7); Ay : out bit_vector(0 to 7));

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