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oepoa aoo a aepe pacpocpae caa coyec oepaop epoo aep after. Hapep, ac Y<= X1&X2 after 20 ns, oaae, o aee caa Y ec epe 20 c oce ee ooo cao X.

Tpacopa aepa peoaae, o ce ee a xoe yy epeaac a xo eaco o pee cyecoa xooo caa. B o coco aoe oe ee o epoo, paoae o py pa. aec p cpo ee caa a xoe oeco cxeo ye oapyeo oo o aee, oopoe ye pcycoa o cee pee aep. coa, ac xooo caa eee pee aep ye "peaa" peeo apa pao. p pacopo aepe peea apaa "xo-xo" ye oee oo, o co co o pee a aee aep. B aece ecoo oce opa oo poec aao c pooo, coe pocxe. Oepaop pacopo aep acaec cey opao: Y<= transport X after ns.

3 MOEPOBAHE OECX CXEM Tpeoa, peee oepoa oecx cxe, a apaeoe oee oepaopo, cooae aepe cao paeee eoo oepoa, peex cxea oao oceoaeoc.

3.1 Moepoae oaox cxe Cxea caec oaoo, ec e e opax ce eeo a.

Moe oaox cxe e VHDL oy oca pa oaa:

oec, apeec, c cooae oepa ooe oepaopo oopeeoo yepe, ycox epexoo oo poeyp. Paccop eoope apa cxe pae coco x pecae.

Ocae oeco cxe, oaao a pc. 3.1, oo peca oec oepaopa: and, or, nand, nor, xor, nxor, not. aepa caa ao eee cocae 20 c.

entity logsh_1 is port (x1, x2, x3, x4: in bit; y: out bit);

end logsh_1;

architecture p1 of logsh_1 is signal e1,e2: bit;

begin e1 <= x1 and x2 after 20 ns; -- apaeoe oee e2 <= x3 xor x4 after 20 ns;

y <= e1 or e2 after 20 ns;

end p1;

Ec ecoo eeo paoa apaeo (pc. 3.2), o oca oo cooa eop:

entity logsh_2 is port (a, b: in bit_vector (0 to 3); y: out bit_vector (0 to 3));

end logsh_architecture p2 of logsh_2 is begin y <= a and b after 20 ns;

end p2;

a0 y& b& a1 yX& bXY y& aX=bXa3 & ybPc.3.1 Puc. 3.1 oceoamea Pc.3.2 apaea opaoa cao oceoaea opaoa cao Puc. 3.2 apaea opaoma a& a=1 bbaa==1 & bb& Y =aa=1 & bb& a3 =ba3 Y =1 & b& Pc.3.3. Cxea oapaopa ab Pc.3.4. Cxea oapaopa ab Puc. 3.3 Cxea onapamopa Puc. 3.4 Cxea onapamopa B x pepax pocxo pa pac oeco cxe oepaop a. o oy peay apy pacpocpae cao, yac aep o cex eeax cxe. oceoaeoc "pac" cxe oepaop popa coaae c oceoaeoc poxoe cao epe ee.

Cxe, peaaee cpae cao, paoaee oepoa oepaopa ooe yopoe. Ha pc. 3.3 oaaa cxea oapaopa, opeeeo opapoe cpaee cao A B. Ec xo o pap ai bi, o a xoe cxe ypoe oeco e, ae ypoe oecoo y.

Cxea, oaaa a pc. 3.4, oe cpaee a b. pae poea oapaopo oe aca e:

entity relat_1 is -- ooee a b port (a, b: in bit_vector (0 to 3); y: out boolean);

end relat_1;

architecture cmp of relat_1 is begin y <= a = b after 40 ns;

end cmp;

entity relat_2 is -- ooee a b port (a, b: in integer range 0 to 3; y: out boolean);

end relat_2;

architecture cmp of relat_2 is begin y <= a >= b after140 ns;

end cmp;

Heocao aoo oca coco o, o pxoc yaa pey aepy cao, pay cye aepe aoo eea. B epo cxee oapaopa a ca poxo a eea, ceoaeo, cyapoe aee 40 c (o 20 ns a a ee). Bo opo cxee acao cyae ca poxo ce eeo.

oece cxe cyaopa ae, a e oee yoe, ee, oee cee oe co oecx eeax pao cxe. poe cyaopa, pye cxe pec pae peo. Tpacop VHDL eae ceay oa, o oo pe ee a ae papao poea.

pocppye oy cyaopa (pc. 3.5) paeo popa c cooae aea oepaopa ea oe:

package add_vect is type small_int is range 0 to 2;

end add_vect ;

use add_vect.all;

entity arithmetic is port (a, b: in small_int; c: out small_int);

end arithmetic;

architecture exmpl of arithmetic is signal c: bit;

begin c <= a + b after 80 ns;

end exmpl;

a=1 cb& & & c1 & & a& & ba=1 =1 cbPc. 3.5 oeca cxea cyaopa Pc.3.5. oeca cxea cyaopa a paee paccopeo pepe, eocao oca coco oepoa aep.

VHDL oeceae oopeee yepe coa ycoo o, yecopo, eyecopo, cxe opa. Cxea, oaaa a pc. 3.6, eo pecaec oepaopo if, a a pc. 3.7 - oepaopo opa case. B peex paeax popa peaoa oceoaeoe oopeeoe yepe cooec c oec cxea.



entity control is port (a, b, c: in boolean; y: out boolean);

end control;

architecture p of control is begin y <= b when a else c;

end p;

paoo ae caa a, b, c, d o oy sel papeaec poxoee a xo y:

entity controls is port (sel: bit_vector (0 to 1); a,b,c,d : bit; y: out bit);

end controls;

architecture p of controls is begin with sel select y <= c when b"00", y <= d when b"01", y <= a when b"10", y <= b when others;

end p;

selsel& c a & & & & y b y & & a & & c & b & d Pc. 3.6 oeca cxea if Pc. 3.7 oeca cxea opa case Pc.3.6. oeca cxea if Pc.3.7. oeca cxea opa case Te e y oy oe c cooae oceoaex yepe yy pocxo yp poecca. coe ycoo oepaope oo oaeo yea a.

Cey pep cppye peee o e aa, o c cooae ycooo oepaopa:

entity control is port (a, b, c: boolean; y: out boolean );

end control;

architecture exmpl of control is begin process (a, b, c) variable n: boolean;

begin if a then n := b;

else n := c;

end if;

y <= n after 60 ns;

end process;

end exmpl;

cooae oepaopa opa ( paoe aaee caa) opyec cpee opaaae oy c ee aepo pacpocpae, e cooae oex ycox oepaopo.

VHDL peye, o ce ooe yco pecae oepaope opa. o apapoa o, coye peoee "pye" oe oepaopa opa, o c e eopeeee yco.

Cey pep cppye ao apa:

entity control is port (sel: bit_vector(0 to 1); a,b,c,d : bit; y: out bit);

end control;

architecture p of control is begin process (sel,a,b,c,d) begin case sel is when b"00" => y <= c;

when b"01" => y <= d;

when b"10" => y <= a;

when others => y <= b;

end case;

end process;

end p;

a& ya& ya& yayPc.3.8. acaoe ee Pc. 3.8 acaoe ee Ec ec oopec pae cxe acaoe ee oaox eeo, o ocaoo opaoa o opopa, e ao cyae ocae oo ooo eea.

Ec ooo, caaa a eeppy aao. ae oa yp a oe copoac cex oox ae aaoo a. o oe e coy peaa eeax cxe.

Paccop pep (pc. 3.8) acaoo e eeo 2. pae popa ao cxe ye e cey opao:

entity loop_sh is port (a: bit_vector(0 to 3); y: out bit_vector(0 to 3));

end loop_sh;

architecture p of loop_sh is begin process (a) variable b:bit;

begin b := '1';

for i in 0 to 3 loop b := a(3-i) and b;

y(i) <= b;

report "Loop number = " & integer'image(i);

end loop;

end process;

end p;

oeco epa oo opaeo; ec oo ye opeec cocoe aoo-o caa, o oo oy ecoe . Byp a oo pacoo eepaop oea e a pae ay epa a.

Cape epc a VHDL e coe cocae oa ca, ooe paoa eocpeceo c a: sll, srl, sla, sra, rol, ror.

ea ac oepaa oe ooep acco a bit boolean, a paa ac - a "eoe". Ec paa ac oepaa - ocaa paee, o ax ec e oec. He pee pae popa c cooae oa ca eo, pao ecoo ca eo.

entity sr_1 is port (a, b,c: in bit_vector (5 downto 0 );

ctl : integer range 0 to 2**5 -1;

w,x,y: out bit_vector (5 downto 0));

end sr_architecture p of sr_1 is begin w <= a sll ctl; -- c eo aoee '0' x <= a sra ctl; -- c pao ac a'left [ a(5) ] y <= a rol ctl; -- ec c eo end p;

Opae pa apaep oaae c epeoae o cpeo apae.

B eoopx cyax p oepoa eoxoo ya pee cocoe eea. oo peycopeo oee caapx aeo std_logic, opeeex ieee. std_logic_1164, cooae ycoo oepaopa null, o paep. ep eo peec oo y std_logic, opo peec oy y. ep eo oo coyec ae.

library ieee;

use ieee.std_logic_1164.all;

entity tbuf is port (enable : boolean;

a : std_logic_vector(0 to 4);

m : out std_logic_vector(0 to 4));

end tbuf;

architecture p of tbuf is begin process (enable, a) if enable then m <= a;

else m <= 'Z';

end if;

end process;

end p;

Ec ao oca ype y, o oo ocooac op eoo.

package p_bus is subtype bundle is bit_vector (0 to 4);

end p_bus;

use work.p_bus.all;

entity tbuf is port (enable: boolean; a: bundle; m: out bundle bus);

end tbuf;

architecture p of tbuf is begin process (enable, a) begin if enable then m <= a;

else m <= null;

end if;

end process;

end p;

peee ycoo oepaopa cay a ae paep. oa ycoo oepaope oc ycoe, ye coppoa yep c pe coco.





3.2 Moepoae oceoaeocx cxe oepoa oceoaeoco o e VHDL e ceax pecypco, oao, paoe cooae oepaopo aepe, oa, oxpax ocpy oax poecco ooe ocaoo xopoo oca cxe aoo a. aa ee cao (po cpe) pecppyec apya a. Oe xopoo coca poe, pe p oca cxe x pecae e oex aoao. B pae popapoa coc opeeee oxo oca apoa cxe ace ax, cpoca ycao coco. aee yy paccope eoope apa x oxoo, ecoeo ex oooc oa yye.

aoe ooe oceoaeoco cxe - o o ecoo oo oaox cxe eoopoe oeco opax ce. aep cao ax cxeax oy apoa (cxpo) ac o pee poxoe caa (acxpoe).

Cocoe cxpox cxe oe oopaac epee, apep, aoee ae cee. Ho acoc o coco cxpopyx cao aee epeeo pcaaec c opeeeo aepo xooy cay. B acxpox cxeax exa opax ce oepyec aaoo cxpo cxea, eec oo ceaa epeeo opao c. cxpox cxe epeea opao c pecae epo aoo aco, a acxpoo cxe - aepy pacpocpae.

O aco coyex oceoaeocx cxeax eeo ec apye pep. Tao pep ee xo ax Data, xo aooo caa Clk, xo aao ycao Reset Set xo xpax ax Q. Tpep epeae ae c xoa a xo oo o poy (ypo cpey) aooo caa. Moepoae ax eeo eecoopao poo c cooae oxpax ocpy oax.

ocaoo e pepa pae popa oe , apep, cey:

D: block ((Clk='1' and not Clk'Stable) or Reset='1') begin Q<=quarded '0' when Reset='1'; else Data when Clk='1' and not Clk'Stable; else Q;

end block D;

B o pepe ae acac o poy Clk. Ec Reset ee co ypoe, o aee pepa cpacaec y. e ee a xoe ocyce epexoa y ey a aoo xoe e e xpaoo pepe ae.

Cey pep cppye ac opa o cay Clk, ocyaey a xo cxe. Oopeeo oec eoopa opaoa xox ax. Bo cex cyax ca "y" coxpae eyee aee, ec e ee ypo aooo caa.

process (Clk, a, b) -- cco cex cao, coyex poecce begin if Clk then y <= a and b;

end if;

end process;

aa pae popa oo paec yp y poeyp a p ao ac cpoax ax. Tao oxo yoe oa, oa eoxoo oepoae apaeo opao cao, apep, oopeeo ca ax pecpe, ocpoeo a ecox pepax.

procedure my_latch (signal Clk, a, b : boolean; signal y : out boolean) begin if Clk then y <= a and b;

end if;

end;

Opaee poeypa, apep, c ee proc_A yp po-ecca oe acao a:

L1: proc_A ( clock, input1, input2, outputA );

L2: proc_A ( clock, input3, input4, outputB );

p aae caa oo cooa ycoe pae. ec ceye opa ae a o, o "y" coyec yx apaex:

y <= a and b when Clk else y;

y <= a and b when Clk;

Ec pep oe ycee poy aooo caa Clk, o ycoe ac ooec apyo, apep:

process (Clk) -- cco cao yceoc begin if Clk and Clk'event then -- opeeee cpea caa y <= a and b;

end if;

end process;

ec ca "y" coxpae aee, ec Clk e eec (e epexoa o y ee).

B oepaope poecca oe ocycoa cco cao yceoc, oa pe oepaop oa oe yco:

process -- e cca cao begin wait until not Clk ; -- oae cpea caa y <= a and b;

end process;

Ec eoxoa apaea opaoa, o, a peye pepe, oe poeypy ae ee p eoxooc:

procedure my_ff (signal Clk, a, b : boolean; signal y : out boolean) begin if not Clk and Clk'event then -- po aooo caa y <= a and b;

end if;

end;

a peye pepe, "y" coyec yapaeo:

y <= a and b when Clk and Clk 'event else y;

y <= a and b when Clk and Clk 'event;

Bxo cpoca ycao ae pepa o ee caa o eo ypo oa oca e y:

function rising_edge (signal s : bit ) return boolean is begin return s = '1' and s'event;

end;

p cooa o y D-pep oe aca a:

q <= d when rising_edge(Clk);

coe poep aooo caa, a pao, pocoe oe a eeape oece oepa, apep, oa ao e oo eee Clk, o ooe ca papee. To e peya ocaec coca yco oepaopo. Ho ax cyax cyecye epooc poyca aooo caa p peex opaex.

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