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Oepa pcoe aa (+, -) - o yape oepa, p oo oopx epe oo oea a Integer Real cac apeec a, ooaa ooeoe opaeoe aee. ox eopo oppoae ooeoo opaoo oa oo pooc cea opopaa ooae. o Integer Real opeee oepa yoe ee (*, /). Ocae oepa, yaae ae (oepa o oy mod, axoe ocaa rem, acooo ae abs oee cee **), e oe y, a caapx ax popapoa.

2.8 acc oeo B e VHDL ec p acca oeo: oca, epeee ca. Oe coaec, oa aec eo ocae. o epe paccope cex x pex acco oeo pee pep oca.

ocmama - o oe, aee oopoo e oe ec. B aece pepo oca oca pee ceye:

constant TIEOFF : MVL := '1', constant OVFL MSG : STRING(1 to 20) := "epeoee ayyopa";

constant INT_VECTOR : bit_vector (0 to 7):= "00001000";

constant Pi : Real :=3.14;

B oca ao oca yaaec ee , aee.

epeee - o oe, ae oopx oy ec. oa o oca coaec eoopa epeea, ece c e coaec a aae "oeep" oo oea.

eee ae epeex ocyecec ye oe oepaopa pcaa epeeo, apep, A:=B + C;. Oepaop pcaa epeex e e peeoo apaepa, .e. x peya caaec eeeo. B c c epeee e e poo oopae aapax cpecax, o oe aopecx pecae. pee eoope pep oca epeex:

variable RUN: Boolean:= False;

variable COUNT: Integer := 0;

variable ADDR: bit_vector (0 to 11);

Ta opao, ocax epeex yaac , , eoaeo, aaoe aee ao epeeo. epeee, coyee oe poecca, cac caec, .e. ccea oepoa coxpae aee ao caeco epeeo o ex op, oa oo e ec oepaopo pcaa. B aece pepa paccop o poecca, coye oepoa pocxe oepaoo aoaeo ycpoca (RAM):

RAM: process (ADDR,RW,CS) type MEMORY is array(0 to 1023) of Bit_vector(0 to 7) variable MEM : MEMORY;

begin --------------- ee a MEM ac a MEM --------------end process RAM;

ocoy epeea MEM ec caeco, acae MEM ae yy coxpac o oea ee ee oepaopo pcaa.

Cua - o oe, ae oopx oy ec oope e peee apaep. ae cao ec oepaopa aae cao, apep, A< = B + C after 50 ns D<=E nor C. Oe, o oepaope aae caa coyec co < =, o o eo o oepaopa pcaa epeeo. B epo pepe oepaopa aae caa yaao "epe 50 c". o oaae, o ca A oe pe pa coe ooe aee cyc 50 c oce eyeo oea pee oepoa. B paax oe oe oee ooo oepaopa aae, ecyeo caa A. Bo opo pepe e pa "after" (epe), o aeo "epe 0 c". Oao oepaop aae cao pec pecae co peax epecx cxeax, a o, ec ae e pa "after" ec peyae ce oaaec, o aec apaep o pa paec y, peoaaec, o a ca pae coe ooe aee c eoopo ea-aepo. ec ea - pooo aoe aee pee, oee y.

Ee oo oe cao o epeex coco o, o ca oy e paep, pe aee aoo caa ec y cex eo paepo. pep ooo cya pee a pc. 2.4. ec oaa a poecca A B, a oopx coep oepaop aae caa X. aoo poecca, pcaaeo aee cay X, coaec paep, cpy peya aoo pcaa. B ao pepe paep e e Dax Dbx. aee caa X cec p oo y papee (ec F). y papee opeee ooae: o cc, oa o paepo aoo caa oyae ooe aee. oce oo aee caa eec a aee, ceoe o y papee .

poecc A y Dax XN F poecc B Ca X Dbx XM Pc. 2.4 pep cxe c o paepa caa ye papee Oepaop pcaa caa pecae coo apae oepaop (a<=b and c m<=In1 when a1 else In2). pcaae a o ypoe paceaec a ocae ooa ax.

Ho eoopx cyax paccapaec a ocae oepoa a ypoe pecpox oepa.

B oaox cxeax oo ax ocaec c oo oepaopa pcaa caa o e pecpoa oepa. B oceoaeocx cxeax oepaop pcaa a ooee yco.

2.9 Apy Apy - o ae, cae c oeoa eeo - oeo e VHDL.

ocpoe oee oepoa ocoeo ay po pa apy. Ec ecoo py apyo, apep, o, acco, cao p. Paccop pyy apyo, opeeey cao:



1 S'last_value (pooe aee S) - peyee aee, oopoe ca S e eocpeceo epe oce eee S. Oocc oy e caoy y, o S.

Moe cooac oo, o poep, e ec a ca.

Hapep, oepaop if S/=S'last_value ooe opopoa eee caa S.

2 S'stable(T) - Boolean. Apy ee coe aee, ec ca S cae eee ocex T e pee. Ec T = 0, apy acaec a S'stable.

3 S'delayed(T) ec aee, oopoe ca S e a T peex e paee. Oocc oy e caoy y, o S.

4 S'event, Boolean, pae coe aee, ec oo o pooo eee caa S.

apy oe oapye ee cao eaoo peeoo oepoa.

Ee o oe aop apyo oocc acca. peoo, apep, o epeea acc a opeeea cey opao:

variable A: bit_vector (0 to 15).

Bo cyae apy e ae, peee a. 2.4:

Taa 2.Apy aee A'range (aao epeeo A) o 0 o A'left (ea paa A) A'right (paa paa A) 2.10 y poeyp B e VHDL ocae y ocyecec a ox ax popapoa.

aaec y , ec eoxoo, xoe apaep. y ee oepaop opaa c opeee o opaaeoo apaepa.

y oe ocaa, apep, cey opao:

function Is_zero(n : Integer) return Boolean is -- ocae o, epeex, oca, opopa begin -- oceoaee oepaop if n=0 then return True;

else return False;

end if;

end;

Bopaaeoe aee oe opeeeo e pae o ceo epe cooecyy oceoaeoc oepaopo. a oeaoc e, oy coaac oae oca, oao, ao poco cyae o e peyec.

VHDL peycapae ae ocae poeyp. poeypa oe e a ypee, a ee apaep. B ocao ocae poeyp aaoo oca y. He oaa pep oca poeyp:

procedure Count (Incr : Boolean; big : out Bit; num : inout Integer) is -- ocae o, epeex, oca, opopa begin if Incr then num := num+1;

end if;

if num >101 then big := '1';

else big := '0';

end if;

end;

Oe, o cce apaepo yaac xoe, xoe apaep. a cco apaepo ceye pae oca. Aop, peaye ao poeypo, - o oceoaeoc oepaopo oce eoo coa begin.

2.11 ae oo, o oc eoc popapoa, e VHDL peycope exa aeo aco coyex oca. aey pcaaec . Oca, coepaec aee, oo cea , aa ccy a a ae. Baae, oao, ae yo oca. pep oooo oca pee e. Oe, o oca aea oy pacoaac o epec y.

-- ocae aea package Pack1 is -- ocae o, oca, cao, opopa end Pack1;

o y coepc ee aea. Ec aee e opopa, ea aea e peyec.

-- ocae ea aea package body Pack1 is -- oppoae opopa end Pack1;

-- ocae epeca entity ID_1 is port(A: in bit_vector(0 to 3); Y: out bit_vector(0 to 9));

end ID_1;

-- oee apxeyp architecture DC of ID_1 is -- ocae o, cao, oca, opopa begin -- apaee oepaop o, poecc end DC;

-- oee oypa configuration Example of ID_1 is -- oypa end Example;

-- oee oe -- coepoe oe e eaec library utils;

-- peoee cooa aae poea -- coepoe oe caoc use utils.all;

use utils.utils_pkg.all;

e ocae aea, peoo, o yo opaoa ocy oy aey co copo oea o ee LogSys. o oo cea yp poea, oec pay use (cooa) epe ocae epeca oea LogSys:

use Pack1.all;

entity LogSys is port(A: in bit_vector(0 to 3); Y: out bit_vector(0 to 9));

end LogSys;

Bo cyae ce (all) oca, coepaec aee Pack1, yy "" oea LogSys, a ce eo apxeype ea.

ae - oe oea ocoeoc a oca aapayp. py papaoo oy cooa caape ae, coepae oca o opopa, oocec poepyeo ccee. oca opopa e ae oe oa. Mexa aeo ocooae papaoa oe o eoxooc oopao o o o. poe oo, ec pye papaoo o oeo coy ecoo ceaco, o oeceaec epoopeoc ax ceo poea.

B e VHDL peycope ae standard (caap), oop oe cooac ce oea. B ce pox ee o ae coep oca o Bit, Bit_vector, Boolean, Integer, Real, Character, String Time, a ae o Positive Natural. Bacoc o epc, coyeo papao poea, oy oac ae std.vhd (caap ae IEEE 1076), ieee. vhd (ae caapo o IEEE 1164), num_bit.mm0 (ae coo o IEEE 1076.3), num_std.mm0 (ae caap coo IEEE 1076.3). oa oa ecoo opa poee ao o oey Vector (library vector;), a ae aca cpoy use std.textio.all, vector.functions.all.





2.12 Oepaop ypae Cpe oepaopo ypae, coyex e VHDL, oo e caape ceae, xapaepe oo aoo a, a, apep, wait. Paccop ocoe aoee aco coyee oepaop ypae.

-- Oepaop if (ec) if increment and not decrement then count := count +1;

elsif not increment and decrement then count := count -1;

elsif increment and decrement then count := 0;

else count := count;

end if;

co oepaope o a Boolean. Booo ae oo ca pa elsif.

pa elsif else c eoae.

Oepaop case (op) pocppye eco pepa.

puep 1 puep case X(0 to 1) is case N is when "00" => Z <= 0; when 0 => Z <= 0;

when "01" => Z <= 1; when 1 => Z <= 1;

when "10" => Z <= not 2; when 2 => Z <= not 2;

when "11" => Z <= Z; when 3 => Z <= 2;

end case; end case;

pep case day is when Saturday to Sunday => work := False;

work_out := False;

when Monday | Wednesday | Friday => work := True;

work_out := True;

when others => work := True;

work_out := False;

end case;

Oepaop opa case ocyece eopoae a ocoe ae ypaeo pae, a ae oe pa oepaop ( pyy oepaopo). B npuepe ypaee paee - o eop, npuepe 2 - eoe, npuepe 3 - cooe. B oe cyae aece ypaeo pae oe cooac o cpe , a oaax pepax, o ooep acc coo.

B e VHDL cyecye oepaop aae caa c opo, oo cea oee cay ac:

with X1&X2&X3 select f <= '0' after 20 ns when "000", '1' after 20 ns when "001", '0' after 20 ns when "010", '1' after 20 ns when "011", '0' after 20 ns when "100", '1' after 20 ns when "101", '1' after 20 ns when "110", '1' after 20 ns when "111";

Oepaop a peay e e y, o o cex ax popapoa. pee epe pepa c cooae oepaopo ypae for, while, loop, next exit:

puep 1 puep for i in 0 to 3 loop Sum: =0;

A(i):= 2** i i:= 1;

end loop; Sum_Int: while i<= n loop Sum:= Sum + 1;

i := i + 1;

end loop Sum_Int;

puep 3 puep Sum:= 0; Sum:= 1;

i:= 0; loop Sum_Int: while i <= N loop VAL(X);

i:= i+1; exit when X <0;

next Sum_Int when i=3; Sum:= Sum + X;

Sum:= Sum + 1; end loop;

end loop Sum_Int;

puep 1 cppye ao for, a npuep 2 - while cooae e a. npuepa 4 ce cyy epx n ex. B npuepe 3 pooc cee o e cao cy, o e ca 3, ocoy a epa poycaec p oo oepaopa next (cey). puep 4 oaae oeao ecoe , oop pae aoeo cye ae, ocyae o-popa. Bxo oo a ye pocxo cyae, oa opopaa VAL(X) ac opaeoe aee. Oepaop for oe paoa opao apae:

L1 : for i in 0 to 9 loop L2 : for j in 0 to 9 loop for k in 4 downto 2 loop -- ooea ea a if k = i next L2; -- cey epexo a ey Lend loop;

exit L1 when j =8; -- xo a ey Lend loop;

end loop;

a ocex oepaopa ypae - return (opa) wait (oae). Oepaop return coyec poeypax yx.

Oepaop oa WAIT coyec pocao poecca a opeee epo pee o oea acye opeeeoo co, apep, wait until clk. oa ocpy oepaopa oa ee :

wait on Sensitivity_list until Condition_clause for Time_out.

aa oepaop pocaaae poecc o oea, oa e ec eoop ca cce yceoc cao (Sensitivity_list). B o pe cc ycoe (Condition_clause), ec peya ee aee "ca", o oee poecca oooec. Macaoe aee pee oa, oce oopoo poecc ooo paoy, yaaec aee Time_out. Heoope yco oy poye, oa oepaop ee eo :

wait on X1,X2; -- poo paoy, oa ec X1 Xwait until (X3=0); -- poo paoy, oa ec X3 1 wait for 100 ns; -- poo paoy epe 100 c.

Bapa oepaopa poecca e cca cao ayca peoaae cooae oepaopa oa c caa ayca, acaeoo ocee cpoo oepaope poecca.

2.13 aep cao B pox cceax ca epeac e oeo, a c eoopo aepo o pee.

p oepoa a e paa a a aepe cao - epoy pacopy. a oec ee, ec paccope peey apay eo pao, oya a xoe aee caa, ae a xo opaoaoe aee epe opeeeoe pe. Caap oec ee, oe o exoo TT, ee aepy 20 c.

oee coe ee, apep, , e pe opa o ycaoeoy apecy 200 - c.

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