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Y(1)<= A(0) and not A(1) and not A(2) and not A(3);

Y(2)<= not A(0) and A(1) and not A(2) and not A(3);

Y(3)<= A(0) and A(1) and not A(2) and not A(3);

Y(4)<= not A(0) and not A(1) and A(2) and not A(3);

Y(5)<= A(0) and not A(1) and A(2) and not A(3);

Y(6)<= not A(0) and A(1) and A(2) and not A(3);

Y(7)<= A(0) and A(1) and A(2) and not A(3);

Y(8)<= not A(0) and not A(1) and not A(2) and A(3);

Y(9)<= A(0) and not A(1) and not A(2) and A(3);

end Level_Mech;

Mooypoe "exa" pecae o opayeae cooae caapo cpyyp peee oecx eeo ax a, , , HE, caee , o e pea cxea.

2.4 Oepaop oo ao eeo oca a e VHDL cy o, .e. opae pae eca, coepa pae oca coe pae. Ceoaeo, apxeypoe eo pecae coo o. Oao paax apxeypoo ea oy cyecoa ypee o. Paccop pep. o A B oe o e o apxeypoo ea. Booo oe co ypoe oeoc, apep, o A Bae oy pa a oo.

cooae ao cpyyp ooe epapxec peca cpyypy oea aca yco "a". Ec ycoe ye e aee "ca", o pape oee opeeex o ypex oepaopo oa. Oxpae ocpy oe oepoa oceoaeoco o.

Hae e epe oepaopo oa oaeo, aee ee oo paccapa a oa. e, apep, L01 aaaec oeoe oe co epe oepaopo oa a peye cpoe. aoe, o ey eo oepaopo oa e o pyx oepaopo.

architecture Block_Structured of System is ---------------- Pae oca o eeo oa begin ----------- Boe oepaop eeo oa A: block ----------- Pae oca o ypeeo oa A begin ----------- Boe oepaop ypeeo oa A end block A;

B: block ----------- Pae oca o ypeeo oa B begin ----------- Boe oepaop ypeeo oa B end block B;

end Block_Structured;

Oepaop oa oe e "oxpaoe" paee oecoo a. Oepaop oxpaeo ocpy ye oc, oa oxpaoe paee ec ca ca pao ac oxpaeoo oepaopa eec eec aee oxpaoo pae ooo coe.

A: block (Clock='1' or Reset='1') begin Y<= guarded '0' when Reset = '1'; -- Reset=else X when Clock='1'; -- Reset=0 Clock=else Y;

end block A;

oa oxpaoe paee ec o, ca, yaa eo ac, coxpae coe peee aee. peeoo pepa p Reset = 0 Clock = 1 xo Y ceye a xoo X. oa cxpoca Clock epec 0, o oceee aee xoa Y acpyec. Cpoc xoa 0 pooe p yco, o Reset = 1. Ta opao coepoao oeee pepa-ae.

2.5 poecc Haoee a eeo oepoa a e VHDL ec oepaop poecca. Oepaop coep oceoaee oepaop ooe papaoy oca cxe a oeeeco ypoe acpa. Hapep:

process (Insig) variable v1: Integer; -- Ocae epeex begin v1 := Insig; -- pcoee epeeo v1 := function_name(v1+1); -- Bo y end process;

p poepoa aapax cpec oepaop poecca peec yx cyax: oaox oceoaeocx cxe. oaox cxe oepaop a:

process (signal1, signal2, , signalN) begin end process;

a oceoaeoco ecoo ae:

process ( X_signal) begin if X_signal and X_signal'event then end if;

end process;

oaox cxe opeeec ec cco ox poecc cao. o a aae cco yceoc cao ayca poecca. Ec ao-o ca oo cca ee coe aee, o poecc apyec oc oepaop oa oo poecca.

oceoaeocx cxe ec cco yceoc, -a ce oepaop pee yco ayca c apya. Ec aoo cca e, o oe oepaop pee wait. Be VHDL peoae oopeeoo oe ec eea cxe peayec p oo exaa poecco. a poecc pecae eoop oec o oepyeo cxe, pe ce poecc oc apaeo. Ec ccea oepoa paoae a o- o poeccope, o, ececeo, aec o yy oc oceoaeo, oao, c o pe oepoa o ye e a, a ec o oc apaeo.

& XZY X& XZXPc. 2.2 pep oeco cxe yc cxea coco pex oecx oo (pc. 2.2). Ec peoo, o xoe aop X1, X2 eea 1 X3, X4 eea apyc oopeeo, o oece ee (o) ae o cpaaa oopeeo. oec o 3 cae a, a oo ec coco a xoe eea 1 (Z1), a xoe eea 2 (Z2).

Ceoaeo, oo cao oe poxo epe ce o oopeeo ae oe opaaac.

B aece opeoo pepa yae, o oece o oy pecae poecca. ec eo aoo poecca coep aae pae oca, e oec epeea oaa aoo poecca.



Boe pae ey e coa begin end coep oepaop pcaa epeeo, oop ce poeyooe aee Zi a oop ceye oepaop aae caa, ya aepy pacpocpae caa oe:

Lb1: process(X1,X2) variable Zi : bit;

begin Zi := X1 and X2;

Z1<= Zi after 20ns;

end process Lb1;

Lb2: process(X3,X4) variable Zi : bit;

begin Zi := X3 and X4;

Z2<= Zi after 20ns;

end process Lb2;

Lb3: process(Z1,Z2) variable Zi : bit;

begin Zi := Z1 or Z2;

Y<= Zi after 20ns;

end process Lb3;

oe poecca oe ae peaoaa aox oepaopax pecpox epea. Paccop ceye a oepaopa pecpox epea:

Y1 = X1 X2;

Y2 = Y1 + X3.

Ta a oepaop acac oceoaeo, o ececeo caa, o oc o yy oceoaeo. aee Y1 coyec a xooe oepaopa Y2.

Hooe aee Y1 pecae coo aec apaep Y2.

Oao oepaop Y1 Y2 oo paccapa c o pe poecco. Cco cao ayca Y1 coep X1 X2, a Y2 - Y1 X3.

ocoy poecc pecae ecy ccey, pe eo oe e oe ye. pep a pc. 2.2 oaae, a opao poeccy oe pcoeo aee aep pacpocpae. p o, ec aoe aee e yaao, ca, o poecc oec a pe, ecoeo aoe, o oee y ( 0). peoo, o ae X1 X3 ec oopeeo oe pee. p o apyc oa poecca. aee Y1 oocc oey pee opeeec ae X1, X2, ec oe pee -. Ceoaeo, ooe aee Y1 p aa poecca o X1 cae ec oe pee +. a oo ec aee Y1, o apyec poecc Y2. Oao poecc Y2 ye ae o ee X3, o aee Y1 o e eco.

B a. 2.1 2.2 pee pep apaeoo oceoaeoo oe oepaopo. B pepe ye ca, o ec oc a e ca eco e.

Taa 2.ae oepaopo aae oe pee Ooaee oepaopo - + + X1 1 4 6 X2 2 2 2 Y1 x 2 8 X3 3 3 5 Y2 x x 5 x - ooaae eopeeeoe cocoe Taa 2.ae oepaopo aae oe pee Ooae oepaopo - + + X1 1 4 6 X2 2 2 2 Y1 2 8 12 X3 3 3 5 Y2 5 11 17 B epo pepe (a. 2.1) ec oc c yeo pee. aee oepaopa ao-o oe pee oe eopeee. p oe ec pocxo epexo ae ooo coa a cey. Bo opo pepe (a. 2.2) eopeeex ae e. ece oec a oopeeo o cey coy cepxy .

2.6 T ax Bo cex ax popapoa yeec ooe ae a ax oepa, poo a a. Tpaoe ax: e, eece, co, oec - coyc e VHDL. Ho ocoy o coyec pecae aapax poeo cax pax apaax, cpeca a ax popea ec ocoeo aoe aee. Hapep, o a papaoy oooc peca pyy a acc o, eoe co eoec o. B e VHDL peaoaa cpoa a; o oaae, o epeyeoe ceee pax o oo oepa ye ocpac a oa. Cpeca cpooo opo o a oooc yo aepe papaoa.

Opee a oeoaoe oeco ae c eoop o xapaepca. o - o ooeco ae aoo a.

T ax yoee accpoa e cxe, oaao a pc. 2.3. T ax ec a cape (ooepe) cocae (ooepe).

Cap ae epec, coo ec . B epeco e poco epecc ce e. Hapep, T Cap Cocao Macc ac ec epec coo Beece e Pc. 2.3 Cxea acca o ax oo cce eo a ceo a - 0 1, pexao o p - 0, 1, Z (cocoe eopeeeoc).

o aa epec , ao aca type BinL is (0, 1) eco o type DecL is (0, 1, 2, 3, 4, 5, 6, 7, 8, 9). epecee pooc cea apao, o aeo a capey. B e aca aaoo opeeec oece . Boolean, Bit, Character e VHDL - o epece . T Boolean coco ae True (ca) False (o). Bce oepaop if (ec) e o poep oe pae oo a. T bit coco ae 0 1.

coo - o e (Integer), o eece (Real). O c caap, a pyx ax popapoa. T Real oe oee cooypoex oeeecx oca, apep, aaoo-pooo epeca aopa opao cao.

Haypae ca (.e. ce eopaee ee ca) coca o Natural a Integer. aao oo opae; apep, e oa Natural e oy opae e. o oe aceoa e aceoa ce aepaece coca poecoo a. Hapep, oa Natural oepa coe yoe opeee, oao, ao cep opae, e ecye. o Positive ae ce ee, oope oe y.





Ocae eoo eeceoo o c aa aaoo ee , apep, a:

type Index is range 0 to 9; -- e type VOLTAGE is range 0.0 to 10.0 -- eece .

ao , e eece, eo opeeec ae aaoa. Beece pecaec ae c aae ao.

a aoee pacpocpaee ece ax oca aapayp coyc apee, ca oa, epeca ooc, acoa.

a VHDL caap ec o ec Time:

type Time is range 0 to 1Eunits fs;

ps = 1000 fs;

ns = 1000 ps;

us = 1000 ns;

ms = 1000 us;

s = 1000 ms;

min = 60 s;

hr = 60 min;

end units;

B aece aoo e paa eoceya (10-15 c) aao o 27,7 . aoy ey pee aao oe pa ooae, oao, aao opaaec o coa cpy-eao a.

Cocae - o acc (ecpye ) ac (cpyyp ). T bit_vector ec acc, oop eo ocaec cey opao:

type bit_vector is array (Natural range < >) of bit;

Bit - o ao eeo acca. Bpaee "Natural range" - caap coco yaa, o a acca ye aaac aaoo aypax ce. ooae oe aaa ope aao p pee aoo a, apep, bit_vector (0 to 3), opaca aao, bit_vector (7 downto 0), ya aao. Boo acc c py ao a.

ac - cocao , coco pa oe. Hapep, IMS oo oca a ac cey opao:

type IMS is record Num : Integer range 1000 to 9900;

Chip: Integer range 8 to 200;

Func: Func_IMS;

end record;

ec Func_IMS - epec , coepa aop y ao pocxe. T Num opeee opo oep pocxe, a Chip opeee opyc oeco oo.

VHDL oocc a co cpo opoe o. ooy oop ye poep e oo cacc cxooo eca, o apoa o cee pax o (oo) a oy. Hapep, ec opee ceye o o epeee:

subtype Address is bit_vector (0 to 15);

subtype Data is bit_vector (0 to 7);

variable Port16: Address;

variable Port8 : Data;

o oee oepaopo Port16:= Port8; Port8:= Port16; ye eep, a a Port16 Portoocc pa oa. Moo opee opo , a eoe co o 0 o 255. Ho oa ao a, o peya oepa a pa oa yy cooecoa y oea ooo yceee ooee y:

subtype Shorter is short range 0 to 31;

subtype Shortest is short range 0 to 15;

signal X1,X2,Y1 : Shortest;

signal Y2 : Shorter;

signal Y3 : short begin Y1 < = X1 + X2; --cya ye yceea Y2 < = X1 + X2; --peya e ee ycee Y3 < = X1 + X2; --peya ee ooee y.

2.7 Oepa VHDL ee o aop oepa pao c peycope a ax.

epee oepa pee a. 2.3.

oece oepa opeee o bit, Boolean ooepx acco, oopx a ee ee bit Boolean; a opao, o opeee a bit_vector.

Bce oepa cpae opaa peya a Boolean, .e. aee True False. Bce oepa cpae e ee pae oepa, apep, A /= B. Oe oepa opo aeoc ( =, /= ) aece eoo paoo oepao oy e o, o o o e . Ec cocao (apep, acc), poepa oec o eo eea. Oa oepaa cocaoo a cac pa, ec pa ce x cooecye ee.

Taa 2.acc oepa e acca not (HE); and (); or (); nand (-HE);

oece nor (-HE); xor (caee ) Cpae =; /=; <; >; <=; >= Coe +; -; & (oaea) pcoe +; aa oee *; /; mod (o oy); rem (ocao) Ceae ** (oeee cee); abs (acooe aee) Oepa ooe (<, < =, >, > =) opeee oo capoo a; apep, epec type MVL is ('0', '1', 'Z') opayeae yopoee cea apao, a o ee eco ooee '1' < 'Z'. Oepa ooe opeec ae ooepx acco, oopx a ee - o cpe . peoo, apep, o oca pexee ooa acc cey opao:

type MVL is ('0','1','Z');

type THREE_bit_MVL is array (0 to 2) of MVL;

B o cyae oepa ooe oy oc a pexee eopa.

Cpaee aaec c aoo ecoo ae pooaec o acaoo.

Ta, apep, aee pae (0, 1, 1) < = (0, Z, 1) ec ca.

Apeece oepa acca coe (+, -) opeee o Integer Real. a bit_vector o e opeee, a o ooae oe ca peycapa opopa o e. Oepa oaea (&) oe co oy y, .e.

oee a ooepx acca c opaoae eoo ooepoo, a oopoo ec cya oox acco-oepao. Ta, apep:

(0, 1, 1) & (0, Z, 1) = (0, 1, 1, 0, Z, 1).

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